1. Field of the Invention
The invention in general relates to the structure and fabrication of integrated circuits and more particularly to an integrated circuit structure and fabrication method in which layered superlattice electronic components can be integrated into conventional MOS technology.
2. Statement of the Problem
It has long been known that ferroelectric materials offer the possibility of simple, low cost, high density, non-volatile memories that are highly resistant to radiation damage and which can be written to and read utilizing the low voltage levels utilized in conventional volatile memories. See for example U.S. patent application Ser. No. 07/919,186 which is hereby incorporated by reference. However, despite over 30 years of research, no ferroelectric memories have had significant commercial success. A key reason for this lack of success has been that ferroelectric materials fatigue relatively rapidly when switched often as typically occurs in a memory. However, recently a new class of materials, called layered superlattice materials, that have as much as 10,000 times the resistance to fatigue as prior ferroelectric materials have been discovered. See U.S. patent application Ser. No. 07/965,190 which is hereby incorporated by reference. Many of these superlattice materials have also been found to have high dielectric constants and low leakage current, which suggests that they should perform well as the dielectric material in otherwise conventional volatile memories.
It would be highly desirable to utilize the new low-fatiguing ferroelectric and high dielectric constant layered superlattice materials in one of the most common, simple, and most dense integrated circuit devices, the DRAM (Dynamic Random Access Memory). DRAM circuits comprise arrays of memory cells, each cell comprising two main components: a field effect transistor (FET) and a capacitor. In the most common Circuit designs, one side of the transistor is connected to one side of the capacitor, and the other side of the transistor and the transistor gate are connected to external connection lines called the bit line and word line, respectively. The other side of the capacitor is connected to a reference voltage. Information is stored in the individual cell by placing a voltage across the capacitor which causes it to store a charge. The transistor provides a switch to access the capacitor. Thus the fabrication of the DRAM cell essentially comprises the fabrication of a transistor, a capacitor, and three contacts to external circuits. If the high dielectric constant layered superlattice materials could be incorporated into capacitors in otherwise conventional silicon DRAM technology, then DRAMs of much higher density could be made. If the low-fatigue ferroelectric layered superlattice materials could be incorporated in the capacitors of conventional silicon DRAMs, then low-fatigue, dense, non-volatile memories would be possible.
However, when known silicon integrated circuit technology is applied to ferroelectric materials, including the layered superlattice materials, either the performance of the ferroelectric materials or the properties of the convention silicon materials tends to degrade. For example, when ferroelectric materials are utilized with a conventional DRAM structure, such as shown in Japanese patent publication 2-304796, some elements of the ferroelectric material tend to diffuse into the silicon devices and alter their performance. Thus in the most successful of the prior art ferroelectric devices, the ferroelectric materials have been separated from the silicon devices by relatively thick diffusion barriers, typically made of silicon nitride. Further, platinum, which is generally compatible with ferroelectrics, is selected as the material adjacent to the ferroelectric material. See for example, U.S. Pat. No. 5,046,043 issued to William D. Miller, et al. Moreover, the ferroelectric layers also have generally been set off at some distance from the silicon devices by thick oxide layers and other layers. The above solution leads directly to a second problem, the fact that platinum tends to peel off of silicon dioxide and other conventional insulators used in silicon technology. This problem is solved by incorporating a thin "adhesive" layer of titanium between the platinum and the insulator. As another example of the incompatibility of the ferroelectric materials With conventional silicon technology, when ferroelectric capacitors have been connected to transistors in the conventional DRAM manner, i.e. by a metal layer connecting the bottom of the capacitor with a transistor source/drain active area on the silicon substrate, the ferroelectric materials have tended to crack; this is believed to be caused by the facts that ferroelectric materials must be annealed at relatively high temperatures, and the connecting metal expands and contracts during the ferroelectric anneal step. One attempted solution to this problem has been the addition of an isolation layer of titanium dioxide. See the Miller patent cited above. However, the titanium introduced in either the adhesive or isolation layer has been found to degrade the performance of layered superlattice materials.
Researchers have also attempted to incorporate ferroelectric materials into gallium arsenide-based integrated circuit technology. However, it has been found that gallium arsenide is unstable at the annealing temperatures of the ferroelectric materials, and arsenic containing gases escape during the annealing process and contaminate the ferroelectric. One attempt to overcome this problem included the complete sealing of the gallium arsenide transistors in a layer of silicon, followed by the formation of the ferroelectric capacitor on an insulating oxide layer deposited over the silicon, and then, after the annealing process and the patterning of the capacitor, the connection of the capacitor to the active area. Since the capacitor is already formed, the connection is made to the upper side of the bottom electrode. See "Process Technology Developments For GaAS Ferroelectric Nonvolatile Memory" by L. E. Sanchez et al., and "Integrated Ferroelectrics" by J. F. Scott et al., in Condensed Matter News, Vol. 1, No. 3, 1992. This process does not appear to be applicable to silicon technology however, not only because silicon does not have the outgassing problem, but also because the resulting structure is highly nonplanar causing problems in applying the metallization layers with conventional technology, such as ion milling. See section 4.3 of the Sanchez paper just cited. Moreover, even if metallization is possible, the conventional silicon integrated circuit structure of transistors deeply imbedded in BPSG and a planarized metallization layer at the surface of the BPSG providing ease in making electrical connection to the integrated circuit components, is not achieved. Compare for example the metallization in the Sanchez paper with the conventional silicon integrated circuit metallization such as shown in VLSI Technology, second edition, edited by S. M. Sze, McGraw-Hill Book Company, Chapter 9, p. 376.
3. Solution to the Problem
The invention solves the above problems by providing an integrated circuit structure and fabrication method in which ferroelectric materials and layered superlattice materials are incorporated into conventional DRAM technology. A conventional MOS transistor is fabricated on a silicon substrate, and conventionally covered with a first insulating layer. Then a capacitor utilizing a layered superlattice material or other ferroelectric material is fabricated and covered with a second insulating layer. Contact holes are opened through the first and second insulating layer, and a wiring layer is deposited to form a conventional DRAM contact structure.
The problem of degradation of the characteristics of the ferroelectric material in the prior art processes is solved by depositing a relatively thin layer of spin-on glass (SOG) over the conventional BPSG first insulating layer. The capacitor is formed on the SOG.
Both electrodes of the capacitor and the intermediate layer of ferroelectric or layered superlattice material are patterned only after the complete capacitor is formed. This has been found to be important in preventing cracking. The electrodes and the intermediate layer may be patterned in any order.
The wiring layer, which tended to cause cracking and peeling problems when the ferroelectric capacitors were formed on it in the prior art, is only formed after the ferroelectric capacitor is deposited, patterned, and encapsulated in a second insulating layer. Preferably, the second insulating layer is also SOG. The portion of the wiring layer contacting the transistor active area penetrates the first and second insulating layers, the portion contacting the capacitor penetrates the second insulating layer, and the portion connecting the contact portions overlies the second insulating layer.
Preferably the wiring layer is multilayered, having a first layer of platinum silicide, a second layer of a metal such as titanium, and a third layer of platinum, although other metals may be used.
In the above structure, SOG completely surrounds the capacitor, except were the wiring layer contacts penetrate the second insulating layer. It has also been found that Si.sub.3 N.sub.4 can be substituted for the SOG in the insulators, although SOG is preferred.
The problem of the degrading of the performance of layered superlattice materials by titanium has been solved by utilizing bottom electrodes consisting essentially of platinum. The SOG/platinum interface does not have the peeling problems of the prior art silicon oxide/platinum interfaces.
Another important factor in eliminating cracking and peeling is a multi-step treating process for the SOG. Preferably the SOG insulator is heated in three or more steps, the temperature of each heating step being at a higher temperature than the previous heating step. Ramping the temperature up and down within each heating step is also beneficial.
The process of making the contact holes for the wiring layer is also important in producing high-quality devices compatible with conventional silicon technology. Preferably, all the contact holes are made in a single process comprising contact hole process steps. That is, intermediate layering steps do not occur between making different contact holes. Preferably, a multiple etch process is used, performing a first etch through a first mask pattern to form a contact hole to the capacitor and initiate the contact hole to the transistor, then performing a second etch through a second etch pattern to complete the contact hole to the transistor active area. Preferably, the contact hole size in said second mask pattern is equal to or smaller than the contact hole size of said first mask pattern. The multiple etch process prevents possible short circuits between the wiring layer and other circuit elements.
It has also been found that the annealing processes are critical in forming high quality devices. The ferroelectric layer is annealed immediately after depositing it, as in the prior art. Preferably each of the capacitor electrodes is also annealed after deposition. Of key importance is an anneal of the second insulating layer prior to deposition of the wiring layer. Preferably, this second insulating layer anneal takes place between the two contact hole etches.
A low temperature anneal, preferably in a mixture of nitrogen and hydrogen gases, between the deposition of the first wiring layer and the second wiring layer returns the MOS devices to substantially their electrical characteristics without the ferroelectric or layered superlattice processes.
The above processes incorporate conventional silicon MOS technology in the processes other than the anneals and bakes. For example, wet etches are used in the contact process. Ion milling is used in the capacitor and metal patterning processes. Conventional MOS materials, such as SOG and BPSG are utilized. The resist and photo processes also are conventional.
In all of the annealing steps, except the MOS recovery annealing step, the MOS circuit is enclosed by thick BPSG and SOG layers. Yet no special isolation or barrier layers, other than the BPSG and SOG which are common in silicon MOS technology, are needed.
In summary, the processes and integrated circuit structures of the invention are much closer to the conventional MOS integrated circuit structures and processes than prior ferroelectric device structures and processes. At the same time, the electronic performance of the individual MOS devices within the integrated circuit fabricated according to the invention is within a few percent of the performance of pure MOS devices, and the electronic performance of the ferroelectric and layered superlattice devices are within 10% of the performance of simple ferroelectric and layered superlattice test devices. Insofar as known, this has never before been accomplished with ferroelectric devices and high dielectric constant materials. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.